IC Failure Analysis market overview
The preparation of ICs for failure analysis, yield enhancement, or reverse engineering requires such techniques as sample deprocessing, and backside silicon access. These techniques can be performed with a plasma etch tool.
The quest for more powerful, smaller, and faster devices increases the need for more metal layers during the chip design and manufacturing processes.
Deprocessing is a challenging effort, as the device must retain electrical integrity, and its surface must remain planar for further investigation on the root causes of the failure.
Semiconductor failure analysis requires techniques to remove the upper layers and intermetal dielectrics of diverse ICs, to expose a defect area that may be located beneath those layers.
From single or multilevel deprocessing without erosion of metallization layers for maintaining electrical investigation, to the most selective and damage free processes for metal etching, CORIAL RIE and ICP-RIE FA solutions enable sample preparation of dies, packaged dies and wafers up to 200 mm.
Delayering capabilities of dies, packaged dies and wafers up to 200 mm
CORIAL processes prevent sample over etch
We have developed a variety of processes to enable individual or multi-layer removal of polymers, silicon compounds, ILD, low and ultra-low-K dielectrics, and metals.
Deprocessing for 28 nm technology node
- Low-K dielectric etching
- Etch rate 300 nm/min
- Selectivity vs. Al/Cu > 50:1
- RIE etch system for deprocessing of dies and packaged dies
- Confined high-density plasma that delivers fast and clean etching of SiO2, Si3N4, and polyimide layers
- Automated EPD to prevent TiN or metals etch
- ICP-RIE etch system for deprocessing of wafers up to 200 mm
- Si, SiO2, Si3N4, low-K/ultra-low-K, polyimide layers deprocessing and backside silicon thinning
- Metal deprocessing capabilities (load-lock required)